Mandatory
- Experience of setting up a Physical Design flow using Synopsys IC Compiler / ASTRO or Cadence SoC Encounter
- Experience on 65nm or below process technology node
- Experience in Low Power Implementation
- Successfully closed Physical Design for at least one SoC
- Strong knowledge of scripting languages (Perl, Shell Programming and TCL)
- EDA Tool
- Synopsys : IC Compiler / ASTRO, PT-SI, Power Compiler OR Cadence : SoC Encounter, ETS, RTL Compiler
Experience : min-4yrs max-7 yrs
