Position: Physical Design Engineer/ Lead / Technical Manager
Location: Bangalore / Pune / Hyderabad / kochi
Experience: 6 - 10 Years
Job Description:
- · Expertise in SoC/VLSI Physical Design.
- · Familiarity with all aspects of chip implementation from RTL to GDS
- · DC Synthesis,
- · ECO implementation,
- · Timing constraints,
- · Timing closure,
- · Physical Design,
- · Floor planning,
- · ICC tool know-how,
- · Physical Verification - Mentor tools, Logic Equivalence Check, Formal verification, Power analysis using Cadence Voltus tool
General
Educational Qualifications
Bachelor's / Master's degree in Electronics/Electrical
Engineering, with concentration on Communications, Signal Processing and VLSI
Design
Digital design of complex SoC IP blocks and
products
Candidate
should possess
- · Strong digital design and VLSI fundamentals Knowledge
- · Expertise in physical design of chips would be desirable
- · Which includes VHDL
- · Verilog
- · C/System
- · C/System-Verilog/Specman,
- · Communication systems & standards (DSL, WLAN, Ethernet), processor IP cores (MIPS, ARC),
- · High-speed interfaces (USB, PCIe, DDR, xGMII)
- ASIC design flow (RTL to GDS) would be desirable
