Job Title: Team Leader DFT
Qualifications:
Required: BE/ME-CS / EEE / ECE with at least 70% marks
Description:
Responsibilities
- Strong fundamental knowledge of DFT techniques for large complex SOCs
- Understanding of core-based test methodology and scan isolation
- Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.
- Knowledge in JTAG, ACJTAG, loop back testing, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
- Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan ATPG tools, Synopsys DFTC scan insertion.
- Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.
•Working knowledge in one or more of the following; C,TCL or Perl. - Experience with industry simulation tools such as VCS, ModelSim, or others.
- Direct experience in silicon bring-up, debug, and validation of DFT features on ATE.
- Detail oriented with strong organizational, problem solving and communication skills.
Skills/Experience
- Experience in design and verification of the above; layout, SPICE simulation, etc.
- Experience with formal verification tools such Verplex, Formality, Conformal,etc.
- Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI.
- Experience with other industry tools such as Vera, Spyglass, 0-in, Jasper, RedHawk, PrimePower.
