Team Leader DFT

Job Title:             Team Leader DFT

Qualifications:     

Required:            BE/ME-CS / EEE / ECE  with at least 70% marks

Description:  

Responsibilities

• Strong fundamental knowledge of DFT techniques for large complex SOCs
• Understanding of core-based test methodology and scan isolation
• Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.
• Knowledge in JTAG, ACJTAG, loop back testing, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
• Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan ATPG tools, Synopsys DFTC scan insertion.
• Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.
  •Working knowledge in one or more of the following; C,TCL or Perl.
• Experience with industry simulation tools such as VCS, ModelSim, or others.
• Direct experience in silicon bring-up, debug, and validation of DFT features on ATE.
• Detail oriented with strong organizational, problem solving and communication skills.

Skills/Experience

• Experience in design and verification of the above; layout, SPICE simulation, etc.
• Experience with formal verification tools such Verplex, Formality, Conformal,etc.
• Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI.
• Experience with other industry tools such as Vera, Spyglass, 0-in, Jasper, RedHawk, PrimePower.

Lead Engineer DFT @Bangalore

Job Description

• Will be responsible for Designing and Implementing DFT techniques. (MemBIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin Mux /Logic BIST) on complex SoC's to improve testability
• Test Modes implementation and verification, scan insertion including on-chip compression.
• Implementing, integrating and verifying memory BIST and boundary scan .
• Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF).
• Basic understanding of complete SoC design and flow.Cross functional teams interaction for issue resolution.
• Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
• Mentoring new team member
• We are looking for a candidate with these specific personal characteristic and qualifications

Experience & Qualification

1. 5 - 11 yrs of experience in DFT
2. Proven experience in the DFT area with both scan and mbist experience.
3. On the scan front, experience should include scan insertion and verification (include ModelSim or VCS simulator) preferably with Synopsys DFTC and TetraMax or Encounter Test experience.
4. On the MBIST front, experience in memory BIST insertion and verification (include ModelSim or VCS simulator).
5. B.Tech / B.E / M.Tech - (Electrical / Electronics/Telecommunication / Any) 

DFT Engineer @Chennai

Required Skills

1. Design For Test experience, Scan insertion, Automatic Test Pattern Generation
2. Awareness of MemBIST flow
3. Familiarity with automatic test equipment
4. EDA Tools à Synopsys, Mentor Graphics (Flextest/fastscan), Atrenta, etc.,
5. Strong Scripting experience using Perl 5

Job description:

• Understanding the overall design
• Preparing a test plan
• Doing scan insertion
• Memory test collar development using tools like MemBIST, 
• Functional pattern generation and verification on design, etc.

Experience: 3 to 5 Years