Job Description
- Will be responsible for Designing and Implementing DFT techniques. (MemBIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin Mux /Logic BIST) on complex SoC's to improve testability
- Test Modes implementation and verification, scan insertion including on-chip compression.
- Implementing, integrating and verifying memory BIST and boundary scan .
- Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF).
- Basic understanding of complete SoC design and flow.Cross functional teams interaction for issue resolution.
- Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
- Mentoring new team member
- We are looking for a candidate with these specific personal characteristic and qualifications
Experience & Qualification
- 5 - 11 yrs of experience in DFT
- Proven experience in the DFT area with both scan and mbist experience.
- On the scan front, experience should include scan insertion and verification (include ModelSim or VCS simulator) preferably with Synopsys DFTC and TetraMax or Encounter Test experience.
- On the MBIST front, experience in memory BIST insertion and verification (include ModelSim or VCS simulator).
- B.Tech / B.E / M.Tech - (Electrical / Electronics/Telecommunication / Any)
