Walk-in Interview for DFT Engineer on 30 July 2016 @Bengaluru

Position:     DFT Engineer
Location:    Bengaluru / Pune / Hyderabad / Kochi
Experince : 4-10 Yrs   

Mandatory Skills

• Good knowledge of Hierarchical scan synthesis
  
• Handle module level scan insertion
• Handle device scan insertion with multiple clock domains. ATPG
• Able to do Block/ Device level pattern generation and simulations
• Scan interleaved with memory BIST patterns gen and validation
• Device level transition delay testing with multiple clocks, handling exceptions
• Able to do Sequential ATPG with RAMs and latches, coverage analysis
  

ViVeda Consulting Services Pvt. Ltd

(M):  91.9963473833 | (O) : 91.40.422.155.00; (F): 91.40.422.155.01 | Url:  www.vivedaglobal.com

Lead Engineer DFT @Bangalore

Job Description

• Will be responsible for Designing and Implementing DFT techniques. (MemBIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin Mux /Logic BIST) on complex SoC's to improve testability
• Test Modes implementation and verification, scan insertion including on-chip compression.
• Implementing, integrating and verifying memory BIST and boundary scan .
• Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF).
• Basic understanding of complete SoC design and flow.Cross functional teams interaction for issue resolution.
• Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
• Mentoring new team member
• We are looking for a candidate with these specific personal characteristic and qualifications

Experience & Qualification

1. 5 - 11 yrs of experience in DFT
2. Proven experience in the DFT area with both scan and mbist experience.
3. On the scan front, experience should include scan insertion and verification (include ModelSim or VCS simulator) preferably with Synopsys DFTC and TetraMax or Encounter Test experience.
4. On the MBIST front, experience in memory BIST insertion and verification (include ModelSim or VCS simulator).
5. B.Tech / B.E / M.Tech - (Electrical / Electronics/Telecommunication / Any) 

DFT Engineer @Chennai

Required Skills

1. Design For Test experience, Scan insertion, Automatic Test Pattern Generation
2. Awareness of MemBIST flow
3. Familiarity with automatic test equipment
4. EDA Tools à Synopsys, Mentor Graphics (Flextest/fastscan), Atrenta, etc.,
5. Strong Scripting experience using Perl 5

Job description:

• Understanding the overall design
• Preparing a test plan
• Doing scan insertion
• Memory test collar development using tools like MemBIST, 
• Functional pattern generation and verification on design, etc.

Experience: 3 to 5 Years